upgrade to IDF v4.3.5

close #35
This commit is contained in:
Karl Osterseher
2023-09-15 10:24:01 +02:00
Unverified
parent 70271e8534
commit 2ed3614bd4
8 changed files with 6342 additions and 259 deletions

View File

@@ -31,7 +31,8 @@
#include "soc/rtc.h"
#include "esp_attr.h"
#include "esp_efuse.h"
#include "soc/chip_revision.h"
#include "hal/efuse_hal.h"
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "esp_log.h"
@@ -184,12 +185,11 @@ static float i2s_apll_get_fi2s(int bits_per_sample, int sdm0, int sdm1,
int f_xtal = (int)rtc_clk_xtal_freq_get() * 1000000;
#if CONFIG_IDF_TARGET_ESP32
/* ESP32 rev0 silicon issue for APLL range/accuracy, please see ESP32 ECO
* document for more information on this */
if (esp_efuse_get_chip_ver() == 0) {
sdm0 = 0;
sdm1 = 0;
}
/* ESP32 rev0 silicon issue for APLL range/accuracy, please see ESP32 ECO document for more information on this */
if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100)) {
sdm0 = 0;
sdm1 = 0;
}
#endif
float fout = f_xtal * (sdm2 + sdm1 / 256.0f + sdm0 / 65536.0f + 4);
if (fout < SOC_I2S_APLL_MIN_FREQ || fout > SOC_I2S_APLL_MAX_FREQ) {

View File

@@ -1,6 +1,8 @@
#ifndef _DSP_PROCESSOR_H_
#define _DSP_PROCESSOR_H_
#include "esp_err.h"
typedef enum dspFlows {
dspfStereo,
dspfBiamp,

View File

@@ -1418,7 +1418,7 @@ static void player_task(void *pvParameters) {
// resync hard if we are getting very late / early.
// rest gets tuned in through apll speed control
if ((msgWaiting == 0) || (MEDIANFILTER_isFull(&shortMedianFilter) &&
(abs(avg) > hardResyncThreshold)))
(abs(shortMedian) > hardResyncThreshold)))
// if (msgWaiting == 0)
{
if (chnk != NULL) {
@@ -1505,8 +1505,7 @@ static void player_task(void *pvParameters) {
// xSemaphoreTake(playerPcmQueueMux, portMAX_DELAY);
// ESP_LOGI (TAG, "%d, %lldus, q %d",
// dir, avg, uxQueueMessagesWaiting(pcmChkQHdl));
//ESP_LOGI (TAG, "%d, %lldus, q %d", dir, avg, uxQueueMessagesWaiting(pcmChkQHdl));
// ESP_LOGI (TAG, "%d, %lldus, %lldus %llds,
// %lld.%lldms", dir, age, avg, sec, msec, usec);